1. Technical Field
The present invention relates generally to the modulation of signals and more particularly to a system for modulating a digital input signal onto a carrier to produce an analog output wherein the system operates at multiple data rates, employs a direct digital synthesis (DDS) operation to produce the analog output signal and provides filtering to reduce system noise and discontinuities in the modulated signal.
2. Related Art
It is well known to modulate signals of interest upon a carrier signal to produce a modulated signal. Typical applications of such modulation include wired and wireless communication systems. A wireless communication system employs a radio frequency (RF) signal upon which signals of interest are carried. Such signals of interest may include voice signals and digitized data. In such systems the data and/or voice signals are modulated onto the RF carrier at a transmitting location and are wirelessly transmitted to a receiving location. At the receiving location, the modulated RF signal is typically down mixed to an intermediate frequency and then demodulated to reproduce the signal of interest.
Many varied methods of modulation are commonly employed in such systems. Such modulation techniques include frequency modulation (FM), amplitude modulation (AM), quadrature amplitude modulation (QAM), phase shift keying (PSK) and frequency shift keying (FSK), along with various other modulation techniques. A particular modification of FSK modulation includes incorporating Gaussian filtering to produce a filtered modulated signal. Gaussian filtering operates to reduce side lobes and other non-carrier frequency components of the modulated signal. Such modulation technique is typically referred to as Gaussian frequency shift keying (GFSK).
In most communication systems, however, the modulation of signals is not a simple task. Problems with modulation result from various factors, not all of which may be contemplated in the design of the modulation circuitry. In one particular application wherein GFSK modulation is used, modulation causes the carrier signal to have a varying frequency, such variation dependent upon the bit pattern modulated onto the carrier. This frequency variation is controlled by the level of a baseband signal. This signal consists of symbols, each of which occupies the same amount of time and represents one or more bits. In a typical GFSK application, a positive peak may be three volts while a negative peak may be negative three volts. In two GFSK operation, wherein a single data bit is modulated onto each symbol period of the carrier signal, a logic zero is represented by a negative three volt peak while a logic one is represented by a positive three volt peak. In four GSFK modulation, wherein two data bits are modulated onto each symbol period of the carrier signal, additional levels are required to represent bit patterns (0,0), (0,1), (1,0) and (1,1). Likewise, in eight GSFK modulation, still further levels are required to represent the still greater number of bit patterns. Thus, the relative frequency of a particular symbol period of the carrier frequency which represents the bit pattern for the particular symbol must be accurately generated.
Thus there exists a need in the art for an improved modulation system supporting multiple data rates while providing smooth transitions between data rates in a modulated output signal.
A multi-rate data modulation circuit constructed according to the present invention includes a multi-rate data conversion circuit and a modulator such as a direct digital synthesis circuit. The multi-rate data conversion circuit receives digital data at varying data rates, receives a data rate input corresponding to the digital data and converts the digital data to a converted output based upon the data rate input. The direct digital synthesis circuit receives the converted output and synthesizes a modulated output signal based upon the converted output.
In one embodiment of the multi-rate data modulation circuit, the multi-rate data conversion circuit includes a multi-rate converter, a multi-rate digital data filter, an output scaler and an adder. The multi-rate converter receives the digital data, the data rate input and a clock signal and converts the digital data to converted digital data. The multi-rate digital data filter receives the converted digital data and produces a filtered digital output. The output scaler receives the filtered digital output and produces a scaled and filtered digital output. Finally, the adder combines the scaled and filtered digital output with a center frequency input and produces the converted output.
In another embodiment of the multi-rate data modulation circuit, the multi-rate digital data filter includes a look-up table that produces filter parameters based upon the converted digital data and that operates at multiple data rates. The multi-rate data modulation circuit may be constructed such that the multi-rate digital data filter includes a digital data filter look-up table, a data rate decode circuit and a plurality of multiplexors. In such case, the data rate decode circuit receives the data rate input and produces control signals therefrom. Each of the plurality of multiplexors receives a portion of the converted digital data and control signals from the data rate decode circuit such that the multiplexors selectively provide the converted digital data to the digital data filter look-up table to produce the filtered digital output.
In accordance with one embodiment of the present invention, the direct digital synthesis circuit may include a phase accumulator, quadrant logic, a direct digital synthesis memory, an unsigned converter and a digital to analog converter. In the construction, the phase accumulator receives the converted output. The quadrant logic couples to the phase accumulator and receives an output of the phase accumulator while the direct digital synthesis memory couples to the quadrant logic and receives an output of the quadrant logic. The unsigned converter couples to the direct digital synthesis memory, receives an output of the direct digital synthesis memory and produces an unsigned output. Finally, the digital to analog converter couples to the unsigned converter, receives the unsigned output and produces the modulated output signal.
In the multi-rate data modulation circuit, the multi-rate data modulation circuit may operate to couple a single bit of data to each symbol period of the modulated output signal during a first time period, to couple two bits of data to each symbol of the modulated output signal during a second time period and to couple three bits of data to each symbol of the modulated output signal during a third time period. The multi-rate data modulation circuit is capable of switching between other sequences of data rates.
The multi-rate data modulation circuit according to the present invention may be installed within a wireless network device, for example. In such case, the wireless network device would include data processing circuitry, the multi-rate data conversion circuit, the direct digital synthesis circuit and a radio. In the wireless network device, the data processing circuitry produces digital data at varying data rates. The multi-rate data conversion circuit receives the digital data at the varying data rates from the data processing circuitry, receives a data rate input corresponding to the digital data and converts the digital data to a converted output based upon the data rate input. The direct digital synthesis circuit then receives the converted output and synthesizes a modulated output signal based upon the converted output. Finally, the radio receives the modulated output signal and transmits the modulated output signal.
In such installation, the wireless network device may also include demodulation circuitry and data conversion circuitry. The demodulation circuitry demodulates the modulated receive signal to produce a demodulated input signal. Further, the data conversion circuitry receives the demodulated input signal, produces converted digital data and transmits the converted digital data to the data processing circuitry.
Moreover, other aspects of the present invention will become apparent with further reference to the drawings and specification which follow.